This invention relates generally to processors and more particularly to an arithmetic shifter contained within such processors and enablement thereof.
Computers are known to include a central processing unit (CPU), system memory, video graphics processing circuitry, audio processing circuitry, modems, and input/output (I/O) ports. The I/O ports allow the central processing unit to interface with peripheral devices such as monitors, keyboards, mouses, printers, the Internet, a local area network, etc. The central processing unit processes applications, which are stored in system memory, in accordance with user inputs to achieve a desired result.
To process the applications, the central processing unit includes circuitry to receive and decode instructions and circuitry to process data in accordance with the decoded instructions. The circuitry to process the data typically includes an arithmetic logic unit (ALU). The arithmetic logic unit performs arithmetic functions such as add, subtract, multiple, divide, shift data, etc. and performs logic functions such as AND, OR, AND, NOR, exclusive OR, etc.
To achieve the data shift function, the arithmetic logic unit includes an arithmetic shifter. One such arithmetic shifter is disclosed in U.S. Pat. No. 5,477,543. The 543 patent teaches a shifter that simultaneously and independently shifts and records a plurality of data bytes. Such a shifter includes first and second registers that each receive a plurality of data bytes. The first register is coupled to a plurality of first buses, with each of the first buses receiving a data byte from the first register. Similarly, the second register is coupled to a plurality of second buses, with each of the second buses receiving a data byte from the second register. A multiplicity of third buses is coupled to the first and second buses. A byte shifting multiplexor is coupled to each of the third buses. A plurality of bit shifting multiplexors are coupled to the byte shifting multiplexors, with each bit shifting multiplexor being coupled to a set of byte shifting multiplexors. A control circuit is coupled to the byte shifting and bit shifting multiplexors. The control circuit provides for independent control of each of the byte shifting multiplexors and each of the bit shifting multiplexors.
The shifter of the 543 patent efficiently produces shifted values, but could be enhanced to provide further functionality by at least preprocessing data before it is received by the shifter. To assist in the preprocessing of data, a byte select vector should be generated.